// (C) Copyright 2012 Kystar. All rights reserved.

`timescale 1ns/100ps
`default_nettype none

module regfile 
(
    input  wire          I_sclk,
    input  wire          I_rst_n,
    //
    input  wire          I_action_wren,
    input  wire          I_cfg_wren,
    input  wire [ 11: 0] I_waddr,
    input  wire [  7: 0] I_wdata,
    //
    input  wire [ 11: 0] I_raddr,
    input  wire          I_status_rden,
    output reg  [  7: 0] O_status_rdata,
    input  wire          I_action_rden,
    output reg  [  7: 0] O_action_rdata,
    input  wire          I_cfg_rden,
    output reg  [  7: 0] O_cfg_rdata,

    // status
    input  wire [  7: 0] I_reg_rb_main_function,         // 0xAA0000
    input  wire [  7: 0] I_reg_rb_sub_function,          // 0xAA0001
    input  wire [  7: 0] I_reg_rb_main_solution,         // 0xAA0002
    input  wire [  7: 0] I_reg_rb_sub_solution,          // 0xAA0003
    input  wire [  7: 0] I_reg_rb_app_type,              // 0xAA0004
    input  wire [  7: 0] I_reg_rb_main_version,          // 0xAA0005
    input  wire [  7: 0] I_reg_rb_sub_version,           // 0xAA0006
    input  wire [  7: 0] I_reg_rb_mini_version,          // 0xAA0007
    input  wire [  7: 0] I_reg_rb_date_year,             // 0xAA0008
    input  wire [  7: 0] I_reg_rb_date_month,            // 0xAA0009
    input  wire [  7: 0] I_reg_rb_date_day,              // 0xAA000A
    input  wire [  7: 0] I_reg_rb_date_clock,            // 0xAA000B
    input  wire          I_reg_rb_video_not_active,      // 0xAA0010
    input  wire [ 12: 0] I_reg_rb_vin_width,             // 0xAA0014
    input  wire [ 12: 0] I_reg_rb_vin_height,            // 0xAA0018
    input  wire [  7: 0] I_reg_rb_vin_frame_rate,        // 0xAA001C
    input  wire          I_reg_rb_c1_calib_done,         // 0xAA0020
    input  wire          I_reg_rb_c3_calib_done,         // 0xAA0024
    input  wire          I_reg_rb_ddr3_err,              // 0xAA0028
    input  wire          I_reg_p0_rb_comm_back_flag,     // 0xAA0030
    input  wire          I_reg_p0_rb_comm_back_crc_err,  // 0xAA0034
    input  wire [ 11: 0] I_reg_p0_rb_comm_back_length,   // 0xAA0038
    input  wire          I_reg_p0_rb_sending_comm_pkg,   // 0xAA003C
    input  wire          I_reg_p1_rb_comm_back_flag,     // 0xAA0040
    input  wire          I_reg_p1_rb_comm_back_crc_err,  // 0xAA0044
    input  wire [ 11: 0] I_reg_p1_rb_comm_back_length,   // 0xAA0048
    input  wire          I_reg_p1_rb_sending_comm_pkg,   // 0xAA004C
    input  wire          I_reg_p2_rb_comm_back_flag,     // 0xAA0050
    input  wire          I_reg_p2_rb_comm_back_crc_err,  // 0xAA0054
    input  wire [ 11: 0] I_reg_p2_rb_comm_back_length,   // 0xAA0058
    input  wire          I_reg_p2_rb_sending_comm_pkg,   // 0xAA005C
    input  wire          I_reg_p3_rb_comm_back_flag,     // 0xAA0060
    input  wire          I_reg_p3_rb_comm_back_crc_err,  // 0xAA0064
    input  wire [ 11: 0] I_reg_p3_rb_comm_back_length,   // 0xAA0068
    input  wire          I_reg_p3_rb_sending_comm_pkg,   // 0xAA006C
    //
    input  wire          I_reg_rb_need_reboot_to_test,   // 0xAA00F0
    // action
    output reg  [ 23: 0] O_reg_reboot_addr,              // 0xAA1000
    output reg           O_reg_reboot_en,                // 0xAA1004
    output reg           O_sc_reg_reset_ddr3,            // 0xAA1008 self-clear
    output reg           O_reg_vib_enable,               // 0xAA100C
    output reg           O_reg_px_enable,                // 0xAA1010
    output reg           O_sc_reg_px_send_comm_pkg,      // 0xAA1014 self-clear
    output reg           O_sc_reg_p0_send_comm_pkg,      // 0xAA1030 self-clear
    output reg           O_sc_reg_p0_clr_comm_back_flag, // 0xAA1034 self-clear
    output reg           O_sc_reg_p1_send_comm_pkg,      // 0xAA1040 self-clear
    output reg           O_sc_reg_p1_clr_comm_back_flag, // 0xAA1044 self-clear
    output reg           O_sc_reg_p2_send_comm_pkg,      // 0xAA1050 self-clear
    output reg           O_sc_reg_p2_clr_comm_back_flag, // 0xAA1054 self-clear
    output reg           O_sc_reg_p3_send_comm_pkg,      // 0xAA1060 self-clear
    output reg           O_sc_reg_p3_clr_comm_back_flag, // 0xAA1064 self-clear
    // cfg
    output reg  [  7: 0] O_reg_nop_bytes,                // 0xAB0000
    output reg  [  8: 0] O_reg_frame_pkg_byte_num,       // 0xAB0004
    output reg  [ 10: 0] O_reg_disp_set_pkg_byte_num,    // 0xAB0008
    output reg  [ 11: 0] O_reg_idle_pkg_byte_num,        // 0xAB000C
    output reg  [ 11: 0] O_reg_comm_pkg_byte_num,        // 0xAB0010
    output reg           O_reg_mac_addr_incr_en,         // 0xAB0014
    output reg  [ 11: 0] O_reg_max_pixel_num_in_one_trans, // 0xAB0018
    output reg           O_reg_long_pkg_en,              // 0xAB001C
    output reg  [ 11: 0] O_reg_px_start_row_offset,      // 0xAB0100
    output reg  [ 11: 0] O_reg_px_start_col_offset,      // 0xAB0104
    output reg  [ 11: 0] O_reg_vin_max_width,            // 0xAB0108
    output reg  [ 11: 0] O_reg_vin_max_height,           // 0xAB010C
    output reg           O_reg_reduced_pkg_en,           // 0xAB0110
    output reg           O_reg_send_card_backup_en,      // 0xAB0114
    // p0
    output reg           O_reg_p0_enable,                // 0xAB0200
    output reg  [ 11: 0] O_reg_p0_start_row,             // 0xAB0204
    output reg  [ 11: 0] O_reg_p0_start_col,             // 0xAB0208
    output reg  [ 11: 0] O_reg_p0_width,                 // 0xAB020C
    output reg  [ 11: 0] O_reg_p0_height,                // 0xAB0210
    output reg           O_reg_p0_disable_disp_set_pkg,  // 0xAB0214
    output reg           O_reg_p0_hori_invert_en,         // 0xAB0218
    output reg           O_reg_p0_vert_invert_en,         // 0xAB021C
    output reg           O_reg_p0_audio_enable,          // 0xAB0220
    output reg  [ 11: 0] O_reg_p0_line_step,             // 0xAB0224
    // p1
    output reg           O_reg_p1_enable,                // 0xAB0300
    output reg  [ 11: 0] O_reg_p1_start_row,             // 0xAB0304
    output reg  [ 11: 0] O_reg_p1_start_col,             // 0xAB0308
    output reg  [ 11: 0] O_reg_p1_width,                 // 0xAB030C
    output reg  [ 11: 0] O_reg_p1_height,                // 0xAB0310
    output reg           O_reg_p1_disable_disp_set_pkg,  // 0xAB0314
    output reg           O_reg_p1_hori_invert_en,         // 0xAB0318
    output reg           O_reg_p1_vert_invert_en,         // 0xAB031C
    output reg           O_reg_p1_audio_enable,          // 0xAB0320
    output reg  [ 11: 0] O_reg_p1_line_step,             // 0xAB0324
    // p2
    output reg           O_reg_p2_enable,                // 0xAB0400
    output reg  [ 11: 0] O_reg_p2_start_row,             // 0xAB0404
    output reg  [ 11: 0] O_reg_p2_start_col,             // 0xAB0408
    output reg  [ 11: 0] O_reg_p2_width,                 // 0xAB040C
    output reg  [ 11: 0] O_reg_p2_height,                // 0xAB0410
    output reg           O_reg_p2_disable_disp_set_pkg,  // 0xAB0414
    output reg           O_reg_p2_hori_invert_en,         // 0xAB0418
    output reg           O_reg_p2_vert_invert_en,         // 0xAB041C
    output reg           O_reg_p2_audio_enable,          // 0xAB0420
    output reg  [ 11: 0] O_reg_p2_line_step,             // 0xAB0424
    // p3
    output reg           O_reg_p3_enable,                // 0xAB0500
    output reg  [ 11: 0] O_reg_p3_start_row,             // 0xAB0504
    output reg  [ 11: 0] O_reg_p3_start_col,             // 0xAB0508
    output reg  [ 11: 0] O_reg_p3_width,                 // 0xAB050C
    output reg  [ 11: 0] O_reg_p3_height,                // 0xAB0510
    output reg           O_reg_p3_disable_disp_set_pkg,  // 0xAB0514
    output reg           O_reg_p3_hori_invert_en,         // 0xAB0518
    output reg           O_reg_p3_vert_invert_en,         // 0xAB051C
    output reg           O_reg_p3_audio_enable,          // 0xAB0520
    output reg  [ 11: 0] O_reg_p3_line_step              // 0xAB0524

);

/******************************************************************************
                                <localparams>
******************************************************************************/

/******************************************************************************
                              <internal signals>
******************************************************************************/
reg  [ 7: 0] last_cfg_wdata;
reg  [ 15: 0] reset_ddr3_dly;

/******************************************************************************
                                <module body>
******************************************************************************/
//--------------------------------------------------------------------
// status
//--------------------------------------------------------------------
always @(posedge I_sclk)
    if (I_status_rden)
        case (I_raddr)
            'h000: O_status_rdata <= I_reg_rb_main_function;               // 0xAA0000
            'h001: O_status_rdata <= I_reg_rb_sub_function;                // 0xAA0001
            'h002: O_status_rdata <= I_reg_rb_main_solution;               // 0xAA0002
            'h003: O_status_rdata <= I_reg_rb_sub_solution;                // 0xAA0003
            'h004: O_status_rdata <= I_reg_rb_app_type;                    // 0xAA0004
            'h005: O_status_rdata <= I_reg_rb_main_version;                // 0xAA0005
            'h006: O_status_rdata <= I_reg_rb_sub_version;                 // 0xAA0006
            'h007: O_status_rdata <= I_reg_rb_mini_version;                // 0xAA0007
            'h008: O_status_rdata <= I_reg_rb_date_year;                   // 0xAA0008
            'h009: O_status_rdata <= I_reg_rb_date_month;                  // 0xAA0009
            'h00A: O_status_rdata <= I_reg_rb_date_day;                    // 0xAA000A
            'h00B: O_status_rdata <= I_reg_rb_date_clock;                  // 0xAA000B
            'h013: O_status_rdata <= I_reg_rb_video_not_active;            // 0xAA0010
            'h016: O_status_rdata <= I_reg_rb_vin_width[12:8];             // 0xAA0014
            'h017: O_status_rdata <= I_reg_rb_vin_width[7:0];              // 0xAA0014
            'h01A: O_status_rdata <= I_reg_rb_vin_height[12:8];            // 0xAA0018
            'h01B: O_status_rdata <= I_reg_rb_vin_height[7:0];             // 0xAA0018
            'h01F: O_status_rdata <= I_reg_rb_vin_frame_rate;              // 0xAA001C
            'h023: O_status_rdata <= I_reg_rb_c1_calib_done;               // 0xAA0020
            'h027: O_status_rdata <= I_reg_rb_c3_calib_done;               // 0xAA0024
            'h02B: O_status_rdata <= I_reg_rb_ddr3_err;                    // 0xAA0028
            'h033: O_status_rdata <= I_reg_p0_rb_comm_back_flag;           // 0xAA0030
            'h037: O_status_rdata <= I_reg_p0_rb_comm_back_crc_err;        // 0xAA0034
            'h03A: O_status_rdata <= I_reg_p0_rb_comm_back_length[11:8];   // 0xAA0038
            'h03B: O_status_rdata <= I_reg_p0_rb_comm_back_length[7:0];    // 0xAA0038
            'h03F: O_status_rdata <= I_reg_p0_rb_sending_comm_pkg;         // 0xAA003C
            'h043: O_status_rdata <= I_reg_p1_rb_comm_back_flag;           // 0xAA0040
            'h047: O_status_rdata <= I_reg_p1_rb_comm_back_crc_err;        // 0xAA0044
            'h04A: O_status_rdata <= I_reg_p1_rb_comm_back_length[11:8];   // 0xAA0048
            'h04B: O_status_rdata <= I_reg_p1_rb_comm_back_length[7:0];    // 0xAA0048
            'h04F: O_status_rdata <= I_reg_p1_rb_sending_comm_pkg;         // 0xAA004C
            'h053: O_status_rdata <= I_reg_p2_rb_comm_back_flag;           // 0xAA0050
            'h057: O_status_rdata <= I_reg_p2_rb_comm_back_crc_err;        // 0xAA0054
            'h05A: O_status_rdata <= I_reg_p2_rb_comm_back_length[11:8];   // 0xAA0058
            'h05B: O_status_rdata <= I_reg_p2_rb_comm_back_length[7:0];    // 0xAA0058
            'h05F: O_status_rdata <= I_reg_p2_rb_sending_comm_pkg;         // 0xAA005C
            'h063: O_status_rdata <= I_reg_p3_rb_comm_back_flag;           // 0xAA0060
            'h067: O_status_rdata <= I_reg_p3_rb_comm_back_crc_err;        // 0xAA0064
            'h06A: O_status_rdata <= I_reg_p3_rb_comm_back_length[11:8];   // 0xAA0068
            'h06B: O_status_rdata <= I_reg_p3_rb_comm_back_length[7:0];    // 0xAA0068
            'h06F: O_status_rdata <= I_reg_p3_rb_sending_comm_pkg;         // 0xAA006C
            'h0F3: O_status_rdata <= I_reg_rb_need_reboot_to_test;         // 0xAA00F0
            default: O_status_rdata <= 'd0;
        endcase

//--------------------------------------------------------------------
// action
//--------------------------------------------------------------------
//    output reg  [ 23: 0] O_reg_reboot_addr,              // 0xAA1000
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_reboot_addr <= 'd0;
    else if (I_action_wren && I_waddr == 'h001)
        O_reg_reboot_addr[23:16] <= I_wdata;
    else if (I_action_wren && I_waddr == 'h002)
        O_reg_reboot_addr[15:8] <= I_wdata;
    else if (I_action_wren && I_waddr == 'h003)
        O_reg_reboot_addr[7:0] <= I_wdata;

//    output reg           O_reg_reboot_en,                // 0xAA1004
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_reboot_en <= 1'b0;
    else if (I_action_wren && I_waddr == 'h007)
        O_reg_reboot_en <= I_wdata;

//    output reg           O_sc_reg_reset_ddr3,               // 0xAA1008 self-clear
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_sc_reg_reset_ddr3 <= 1'b0;
    else if (reset_ddr3_dly[15])
        O_sc_reg_reset_ddr3 <= 1'b0;
    else if (I_action_wren && I_waddr == 'h00B)
        O_sc_reg_reset_ddr3 <= I_wdata;

always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        reset_ddr3_dly <= 'd0;
    else
        reset_ddr3_dly <= {reset_ddr3_dly[14:0],O_sc_reg_reset_ddr3};

//    output reg           O_reg_vib_enable,               // 0xAA100C
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_vib_enable <= 1'b0;
    else if (I_action_wren && I_waddr == 'h00F)
        O_reg_vib_enable <= I_wdata;

//    output reg           O_reg_px_enable,                // 0xAA1010
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_px_enable <= 1'b0;
    else if (I_action_wren && I_waddr == 'h013)
        O_reg_px_enable <= I_wdata;

//    output reg           O_sc_reg_px_send_comm_pkg,         // 0xAA1014 self-clear
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_sc_reg_px_send_comm_pkg <= 1'b0;
    else if (O_sc_reg_px_send_comm_pkg)
        O_sc_reg_px_send_comm_pkg <= 1'b0;
    else if (I_action_wren && I_waddr == 'h017)
        O_sc_reg_px_send_comm_pkg <= I_wdata;

//    output reg           O_sc_reg_p0_send_comm_pkg,         // 0xAA1030 self-clear
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_sc_reg_p0_send_comm_pkg <= 1'b0;
    else if (O_sc_reg_p0_send_comm_pkg)
        O_sc_reg_p0_send_comm_pkg <= 1'b0;
    else if (I_action_wren && I_waddr == 'h033)
        O_sc_reg_p0_send_comm_pkg <= I_wdata;

//    output reg           O_sc_reg_p0_clr_comm_back_flag,    // 0xAA1034 self-clear
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_sc_reg_p0_clr_comm_back_flag <= 1'b0;
    else if (O_sc_reg_p0_clr_comm_back_flag)
        O_sc_reg_p0_clr_comm_back_flag <= 1'b0;
    else if (I_action_wren && I_waddr == 'h037)
        O_sc_reg_p0_clr_comm_back_flag <= I_wdata;

//    output reg           O_sc_reg_p1_send_comm_pkg,         // 0xAA1040 self-clear
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_sc_reg_p1_send_comm_pkg <= 1'b0;
    else if (O_sc_reg_p1_send_comm_pkg)
        O_sc_reg_p1_send_comm_pkg <= 1'b0;
    else if (I_action_wren && I_waddr == 'h043)
        O_sc_reg_p1_send_comm_pkg <= I_wdata;

//    output reg           O_sc_reg_p1_clr_comm_back_flag,    // 0xAA1044 self-clear
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_sc_reg_p1_clr_comm_back_flag <= 1'b0;
    else if (O_sc_reg_p1_clr_comm_back_flag)
        O_sc_reg_p1_clr_comm_back_flag <= 1'b0;
    else if (I_action_wren && I_waddr == 'h047)
        O_sc_reg_p1_clr_comm_back_flag <= I_wdata;

//    output reg           O_sc_reg_p2_send_comm_pkg,         // 0xAA1050 self-clear
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_sc_reg_p2_send_comm_pkg <= 1'b0;
    else if (O_sc_reg_p2_send_comm_pkg)
        O_sc_reg_p2_send_comm_pkg <= 1'b0;
    else if (I_action_wren && I_waddr == 'h053)
        O_sc_reg_p2_send_comm_pkg <= I_wdata;

//    output reg           O_sc_reg_p2_clr_comm_back_flag,    // 0xAA1054 self-clear
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_sc_reg_p2_clr_comm_back_flag <= 1'b0;
    else if (O_sc_reg_p2_clr_comm_back_flag)
        O_sc_reg_p2_clr_comm_back_flag <= 1'b0;
    else if (I_action_wren && I_waddr == 'h057)
        O_sc_reg_p2_clr_comm_back_flag <= I_wdata;

//    output reg           O_sc_reg_p3_send_comm_pkg,         // 0xAA1060 self-clear
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_sc_reg_p3_send_comm_pkg <= 1'b0;
    else if (O_sc_reg_p3_send_comm_pkg)
        O_sc_reg_p3_send_comm_pkg <= 1'b0;
    else if (I_action_wren && I_waddr == 'h063)
        O_sc_reg_p3_send_comm_pkg <= I_wdata;

//    output reg           O_sc_reg_p3_clr_comm_back_flag,    // 0xAA1064 self-clear
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_sc_reg_p3_clr_comm_back_flag <= 1'b0;
    else if (O_sc_reg_p3_clr_comm_back_flag)
        O_sc_reg_p3_clr_comm_back_flag <= 1'b0;
    else if (I_action_wren && I_waddr == 'h067)
        O_sc_reg_p3_clr_comm_back_flag <= I_wdata;

always @(posedge I_sclk)
    if (I_action_rden)
        case (I_raddr)
            'h001: O_action_rdata <= O_reg_reboot_addr[23:16];       // 0xAA1000
            'h002: O_action_rdata <= O_reg_reboot_addr[15:8];        // 0xAA1000
            'h003: O_action_rdata <= O_reg_reboot_addr[7:0];         // 0xAA1000
            'h00F: O_action_rdata <= O_reg_vib_enable;               // 0xAA100C
            'h013: O_action_rdata <= O_reg_px_enable;                // 0xAA1010
            default: O_action_rdata <= 'd0;
        endcase

//--------------------------------------------------------------------
// cfg
//--------------------------------------------------------------------
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        last_cfg_wdata <= 'd0;
    else if (I_cfg_wren)
        last_cfg_wdata<= I_wdata;

//    output reg  [  7: 0] O_reg_nop_bytes,                // 0xAB0000
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_nop_bytes <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h003)
        O_reg_nop_bytes <= I_wdata;

//    output reg  [  8: 0] O_reg_frame_pkg_byte_num,       // 0xAB0004
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_frame_pkg_byte_num <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h007)
        O_reg_frame_pkg_byte_num <= {last_cfg_wdata,I_wdata};

//    output reg  [ 10: 0] O_reg_disp_set_pkg_byte_num,    // 0xAB0008
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_disp_set_pkg_byte_num <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h00B)
        O_reg_disp_set_pkg_byte_num <= {last_cfg_wdata,I_wdata};

//    output reg  [ 11: 0] O_reg_idle_pkg_byte_num,        // 0xAB000C
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_idle_pkg_byte_num <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h00F)
        O_reg_idle_pkg_byte_num <= {last_cfg_wdata,I_wdata};

//    output reg  [ 11: 0] O_reg_comm_pkg_byte_num,        // 0xAB0010
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_comm_pkg_byte_num <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h013)
        O_reg_comm_pkg_byte_num <= {last_cfg_wdata,I_wdata};

//    output reg           O_reg_mac_addr_incr_en,         // 0xAB0014
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_mac_addr_incr_en <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h017)
        O_reg_mac_addr_incr_en <= I_wdata;

//    output reg  [ 11: 0] O_reg_max_pixel_num_in_one_trans, // 0xAB0018
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_max_pixel_num_in_one_trans <= 'd480;
    else if (I_cfg_wren && I_waddr == 'h01B)
        O_reg_max_pixel_num_in_one_trans <= {last_cfg_wdata,I_wdata};

//    output reg           O_reg_long_pkg_en,              // 0xAB001C
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_long_pkg_en <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h01F)
        O_reg_long_pkg_en <= I_wdata;

//    output reg  [ 11: 0] O_reg_px_start_row_offset,      // 0xAB0100
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_px_start_row_offset <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h103)
        O_reg_px_start_row_offset <= {last_cfg_wdata,I_wdata};

//    output reg  [ 11: 0] O_reg_px_start_col_offset,      // 0xAB0104
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_px_start_col_offset <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h107)
        O_reg_px_start_col_offset <= {last_cfg_wdata,I_wdata};

//    output reg  [ 11: 0] O_reg_vin_max_width,            // 0xAB0108
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_vin_max_width <= 4095;
    else if (I_cfg_wren && I_waddr == 'h10B)
        O_reg_vin_max_width <= {last_cfg_wdata,I_wdata};

//    output reg  [ 11: 0] O_reg_vin_max_height,            // 0xAB010C
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_vin_max_height <= 2048;
    else if (I_cfg_wren && I_waddr == 'h10F)
        O_reg_vin_max_height <= {last_cfg_wdata,I_wdata};

//    output reg           O_reg_reduced_pkg_en,           // 0xAB0110
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_reduced_pkg_en <= 0;
    else if (I_cfg_wren && I_waddr == 'h113)
        O_reg_reduced_pkg_en <= I_wdata;

//    output reg           O_reg_send_card_backup_en,       // 0xAB0114
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_send_card_backup_en <= 0;
    else if (I_cfg_wren && I_waddr == 'h117)
        O_reg_send_card_backup_en <= I_wdata;

//    output reg           O_reg_p0_enable,                // 0xAB0200
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p0_enable <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h203)
        O_reg_p0_enable <= I_wdata;

//    output reg  [ 11: 0] O_reg_p0_start_row,             // 0xAB0204
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p0_start_row <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h207)
        O_reg_p0_start_row <= {last_cfg_wdata,I_wdata};

//    output reg  [ 11: 0] O_reg_p0_start_col,             // 0xAB0208
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p0_start_col <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h20B)
        O_reg_p0_start_col <= {last_cfg_wdata,I_wdata};

//    output reg  [ 11: 0] O_reg_p0_width,                 // 0xAB020C
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p0_width <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h20F)
        O_reg_p0_width <= {last_cfg_wdata,I_wdata};

//    output reg  [ 11: 0] O_reg_p0_height,                // 0xAB0210
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p0_height <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h213)
        O_reg_p0_height <= {last_cfg_wdata,I_wdata};

//    output reg           O_reg_p0_disable_disp_set_pkg,  // 0xAB0214
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p0_disable_disp_set_pkg <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h217)
        O_reg_p0_disable_disp_set_pkg <= I_wdata;

//    output reg           O_reg_p0_hori_invert_en,         // 0xAB0218
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p0_hori_invert_en <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h21B)
        O_reg_p0_hori_invert_en <= I_wdata;

//    output reg           O_reg_p0_vert_invert_en,         // 0xAB021C
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p0_vert_invert_en <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h21F)
        O_reg_p0_vert_invert_en <= I_wdata;

//    output reg           O_reg_p0_audio_enable,          // 0xAB0220
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p0_audio_enable <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h223)
        O_reg_p0_audio_enable <= I_wdata;

//    output reg  [ 11: 0] O_reg_p0_line_step,             // 0xAB0224
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p0_line_step <= 'd1;
    else if (I_cfg_wren && I_waddr == 'h227)
        O_reg_p0_line_step <= {last_cfg_wdata,I_wdata};

//    output reg           O_reg_p1_enable,                // 0xAB0300
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p1_enable <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h303)
        O_reg_p1_enable <= I_wdata;

//    output reg  [ 11: 0] O_reg_p1_start_row,             // 0xAB0304
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p1_start_row <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h307)
        O_reg_p1_start_row <= {last_cfg_wdata,I_wdata};

//    output reg  [ 11: 0] O_reg_p1_start_col,             // 0xAB0308
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p1_start_col <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h30B)
        O_reg_p1_start_col <= {last_cfg_wdata,I_wdata};

//    output reg  [ 11: 0] O_reg_p1_width,                 // 0xAB030C
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p1_width <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h30F)
        O_reg_p1_width <= {last_cfg_wdata,I_wdata};

//    output reg  [ 11: 0] O_reg_p1_height,                // 0xAB0310
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p1_height <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h313)
        O_reg_p1_height <= {last_cfg_wdata,I_wdata};

//    output reg           O_reg_p1_disable_disp_set_pkg,  // 0xAB0314
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p1_disable_disp_set_pkg <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h317)
        O_reg_p1_disable_disp_set_pkg <= I_wdata;

//    output reg           O_reg_p1_hori_invert_en,         // 0xAB0318
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p1_hori_invert_en <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h31B)
        O_reg_p1_hori_invert_en <= I_wdata;

//    output reg           O_reg_p1_vert_invert_en,         // 0xAB031C
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p1_vert_invert_en <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h31F)
        O_reg_p1_vert_invert_en <= I_wdata;

//    output reg           O_reg_p1_audio_enable,          // 0xAB0320
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p1_audio_enable <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h323)
        O_reg_p1_audio_enable <= I_wdata;

//    output reg  [ 11: 0] O_reg_p1_line_step,             // 0xAB0324
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p1_line_step <= 'd1;
    else if (I_cfg_wren && I_waddr == 'h327)
        O_reg_p1_line_step <= {last_cfg_wdata,I_wdata};

//    output reg           O_reg_p2_enable,                // 0xAB0400
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p2_enable <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h403)
        O_reg_p2_enable <= I_wdata;

//    output reg  [ 11: 0] O_reg_p2_start_row,             // 0xAB0404
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p2_start_row <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h407)
        O_reg_p2_start_row <= {last_cfg_wdata,I_wdata};

//    output reg  [ 11: 0] O_reg_p2_start_col,             // 0xAB0408
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p2_start_col <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h40B)
        O_reg_p2_start_col <= {last_cfg_wdata,I_wdata};

//    output reg  [ 11: 0] O_reg_p2_width,                 // 0xAB040C
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p2_width <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h40F)
        O_reg_p2_width <= {last_cfg_wdata,I_wdata};

//    output reg  [ 11: 0] O_reg_p2_height,                // 0xAB0410
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p2_height <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h413)
        O_reg_p2_height <= {last_cfg_wdata,I_wdata};

//    output reg           O_reg_p2_disable_disp_set_pkg,  // 0xAB0414
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p2_disable_disp_set_pkg <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h417)
        O_reg_p2_disable_disp_set_pkg <= I_wdata;

//    output reg           O_reg_p2_hori_invert_en,         // 0xAB0418
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p2_hori_invert_en <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h41B)
        O_reg_p2_hori_invert_en <= I_wdata;

//    output reg           O_reg_p2_vert_invert_en,         // 0xAB041C
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p2_vert_invert_en <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h41F)
        O_reg_p2_vert_invert_en <= I_wdata;

//    output reg           O_reg_p2_audio_enable,          // 0xAB0420
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p2_audio_enable <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h423)
        O_reg_p2_audio_enable <= I_wdata;

//    output reg  [ 11: 0] O_reg_p2_line_step,             // 0xAB0424
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p2_line_step <= 'd1;
    else if (I_cfg_wren && I_waddr == 'h427)
        O_reg_p2_line_step <= {last_cfg_wdata,I_wdata};

//    output reg           O_reg_p3_enable,                // 0xAB0500
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p3_enable <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h503)
        O_reg_p3_enable <= I_wdata;

//    output reg  [ 11: 0] O_reg_p3_start_row,             // 0xAB0504
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p3_start_row <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h507)
        O_reg_p3_start_row <= {last_cfg_wdata,I_wdata};

//    output reg  [ 11: 0] O_reg_p3_start_col,             // 0xAB0508
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p3_start_col <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h50B)
        O_reg_p3_start_col <= {last_cfg_wdata,I_wdata};

//    output reg  [ 11: 0] O_reg_p3_width,                 // 0xAB050C
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p3_width <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h50F)
        O_reg_p3_width <= {last_cfg_wdata,I_wdata};

//    output reg  [ 11: 0] O_reg_p3_height,                // 0xAB0510
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p3_height <= 'd0;
    else if (I_cfg_wren && I_waddr == 'h513)
        O_reg_p3_height <= {last_cfg_wdata,I_wdata};

//    output reg           O_reg_p3_disable_disp_set_pkg   // 0xAB0514
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p3_disable_disp_set_pkg <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h517)
        O_reg_p3_disable_disp_set_pkg <= I_wdata;

//    output reg           O_reg_p3_hori_invert_en,         // 0xAB0518
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p3_hori_invert_en <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h51B)
        O_reg_p3_hori_invert_en <= I_wdata;

//    output reg           O_reg_p3_vert_invert_en,         // 0xAB051C
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p3_vert_invert_en <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h51F)
        O_reg_p3_vert_invert_en <= I_wdata;

//    output reg           O_reg_p3_audio_enable,          // 0xAB0520
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p3_audio_enable <= 1'b0;
    else if (I_cfg_wren && I_waddr == 'h523)
        O_reg_p3_audio_enable <= I_wdata;

//    output reg  [ 11: 0] O_reg_p3_line_step,             // 0xAB0524
always @(posedge I_sclk or negedge I_rst_n)
    if (!I_rst_n)
        O_reg_p3_line_step <= 'd1;
    else if (I_cfg_wren && I_waddr == 'h527)
        O_reg_p3_line_step <= {last_cfg_wdata,I_wdata};

always @(posedge I_sclk)
    if (I_cfg_rden)
        case (I_raddr)
            'h003: O_cfg_rdata <= O_reg_nop_bytes;                  // 0xAB0000
            'h006: O_cfg_rdata <= O_reg_frame_pkg_byte_num[8];      // 0xAB0004
            'h007: O_cfg_rdata <= O_reg_frame_pkg_byte_num[7:0];    // 0xAB0004
            'h00A: O_cfg_rdata <= O_reg_disp_set_pkg_byte_num[10:8];// 0xAB0008
            'h00B: O_cfg_rdata <= O_reg_disp_set_pkg_byte_num[7:0]; // 0xAB0008
            'h00E: O_cfg_rdata <= O_reg_idle_pkg_byte_num[11:8];    // 0xAB000C
            'h00F: O_cfg_rdata <= O_reg_idle_pkg_byte_num[7:0];     // 0xAB000C
            'h012: O_cfg_rdata <= O_reg_comm_pkg_byte_num[11:8];    // 0xAB0010
            'h013: O_cfg_rdata <= O_reg_comm_pkg_byte_num[7:0];     // 0xAB0010
            'h017: O_cfg_rdata <= O_reg_mac_addr_incr_en;           // 0xAB0014
            'h01A: O_cfg_rdata <= O_reg_max_pixel_num_in_one_trans[11:8]; // 0xAB0018
            'h01B: O_cfg_rdata <= O_reg_max_pixel_num_in_one_trans[7:0];  // 0xAB0018
            'h01F: O_cfg_rdata <= O_reg_long_pkg_en;                // 0xAB001C
            'h102: O_cfg_rdata <= O_reg_px_start_row_offset[11:8];  // 0xAB0100
            'h103: O_cfg_rdata <= O_reg_px_start_row_offset[7:0];   // 0xAB0100
            'h106: O_cfg_rdata <= O_reg_px_start_col_offset[11:8];  // 0xAB0104
            'h107: O_cfg_rdata <= O_reg_px_start_col_offset[7:0];   // 0xAB0104
            'h10A: O_cfg_rdata <= O_reg_vin_max_width[11:8];        // 0xAB0108
            'h10B: O_cfg_rdata <= O_reg_vin_max_width[7:0];         // 0xAB0108
            'h10E: O_cfg_rdata <= O_reg_vin_max_height[11:8];       // 0xAB010C
            'h10F: O_cfg_rdata <= O_reg_vin_max_height[7:0];        // 0xAB010C
            'h113: O_cfg_rdata <= O_reg_reduced_pkg_en;             // 0xAB0110
            'h117: O_cfg_rdata <= O_reg_send_card_backup_en;        // 0xAB0114
            // p0
            'h203: O_cfg_rdata <= O_reg_p0_enable;                  // 0xAB0200
            'h206: O_cfg_rdata <= O_reg_p0_start_row[11:8];         // 0xAB0204
            'h207: O_cfg_rdata <= O_reg_p0_start_row[7:0];          // 0xAB0204
            'h20A: O_cfg_rdata <= O_reg_p0_start_col[11:8];         // 0xAB0208
            'h20B: O_cfg_rdata <= O_reg_p0_start_col[7:0];          // 0xAB0208
            'h20E: O_cfg_rdata <= O_reg_p0_width[11:8];             // 0xAB020C
            'h20F: O_cfg_rdata <= O_reg_p0_width[7:0];              // 0xAB020C
            'h212: O_cfg_rdata <= O_reg_p0_height[11:8];            // 0xAB0210
            'h213: O_cfg_rdata <= O_reg_p0_height[7:0];             // 0xAB0210
            'h217: O_cfg_rdata <= O_reg_p0_disable_disp_set_pkg;    // 0xAB0214
            'h218: O_cfg_rdata <= O_reg_p0_hori_invert_en;           // 0xAB0218
            'h21F: O_cfg_rdata <= O_reg_p0_vert_invert_en;           // 0xAB021C
            'h223: O_cfg_rdata <= O_reg_p0_audio_enable;            // 0xAB0220
            'h226: O_cfg_rdata <= O_reg_p0_line_step[11:8];         // 0xAB0224
            'h227: O_cfg_rdata <= O_reg_p0_line_step[7:0];          // 0xAB0224
            // p1
            'h303: O_cfg_rdata <= O_reg_p1_enable;                  // 0xAB0300
            'h306: O_cfg_rdata <= O_reg_p1_start_row[11:8];         // 0xAB0304
            'h307: O_cfg_rdata <= O_reg_p1_start_row[7:0];          // 0xAB0304
            'h30A: O_cfg_rdata <= O_reg_p1_start_col[11:8];         // 0xAB0308
            'h30B: O_cfg_rdata <= O_reg_p1_start_col[7:0];          // 0xAB0308
            'h30E: O_cfg_rdata <= O_reg_p1_width[11:8];             // 0xAB030C
            'h30F: O_cfg_rdata <= O_reg_p1_width[7:0];              // 0xAB030C
            'h312: O_cfg_rdata <= O_reg_p1_height[11:8];            // 0xAB0310
            'h313: O_cfg_rdata <= O_reg_p1_height[7:0];             // 0xAB0310
            'h317: O_cfg_rdata <= O_reg_p1_disable_disp_set_pkg;    // 0xAB0314
            'h318: O_cfg_rdata <= O_reg_p1_hori_invert_en;           // 0xAB0318
            'h31F: O_cfg_rdata <= O_reg_p1_vert_invert_en;           // 0xAB031C
            'h323: O_cfg_rdata <= O_reg_p1_audio_enable;            // 0xAB0320
            'h326: O_cfg_rdata <= O_reg_p1_line_step[11:8];         // 0xAB0324
            'h327: O_cfg_rdata <= O_reg_p1_line_step[7:0];          // 0xAB0324
            // p2
            //'h403: O_cfg_rdata <= O_reg_p2_enable;                  // 0xAB0400
            //'h406: O_cfg_rdata <= O_reg_p2_start_row[11:8];         // 0xAB0404
            //'h407: O_cfg_rdata <= O_reg_p2_start_row[7:0];          // 0xAB0404
            //'h40A: O_cfg_rdata <= O_reg_p2_start_col[11:8];         // 0xAB0408
            //'h40B: O_cfg_rdata <= O_reg_p2_start_col[7:0];          // 0xAB0408
            //'h40E: O_cfg_rdata <= O_reg_p2_width[11:8];             // 0xAB040C
            //'h40F: O_cfg_rdata <= O_reg_p2_width[7:0];              // 0xAB040C
            //'h412: O_cfg_rdata <= O_reg_p2_height[11:8];            // 0xAB0410
            //'h413: O_cfg_rdata <= O_reg_p2_height[7:0];             // 0xAB0410
            //'h417: O_cfg_rdata <= O_reg_p2_disable_disp_set_pkg;    // 0xAB0414
            //'h418: O_cfg_rdata <= O_reg_p2_hori_invert_en;           // 0xAB0418
            //'h41F: O_cfg_rdata <= O_reg_p2_vert_invert_en;           // 0xAB041C
            //'h423: O_cfg_rdata <= O_reg_p2_audio_enable;            // 0xAB0420
            //'h426: O_cfg_rdata <= O_reg_p2_line_step[11:8];         // 0xAB0424
            //'h427: O_cfg_rdata <= O_reg_p2_line_step[7:0];          // 0xAB0424
            // p3
            //'h503: O_cfg_rdata <= O_reg_p3_enable;                  // 0xAB0500
            //'h506: O_cfg_rdata <= O_reg_p3_start_row[11:8];         // 0xAB0504
            //'h507: O_cfg_rdata <= O_reg_p3_start_row[7:0];          // 0xAB0504
            //'h50A: O_cfg_rdata <= O_reg_p3_start_col[11:8];         // 0xAB0508
            //'h50B: O_cfg_rdata <= O_reg_p3_start_col[7:0];          // 0xAB0508
            //'h50E: O_cfg_rdata <= O_reg_p3_width[11:8];             // 0xAB050C
            //'h50F: O_cfg_rdata <= O_reg_p3_width[7:0];              // 0xAB050C
            //'h512: O_cfg_rdata <= O_reg_p3_height[11:8];            // 0xAB0510
            //'h513: O_cfg_rdata <= O_reg_p3_height[7:0];             // 0xAB0510
            //'h517: O_cfg_rdata <= O_reg_p3_disable_disp_set_pkg;    // 0xAB0514
            //'h518: O_cfg_rdata <= O_reg_p3_hori_invert_en;           // 0xAB0518
            //'h51F: O_cfg_rdata <= O_reg_p3_vert_invert_en;           // 0xAB051C
            //'h523: O_cfg_rdata <= O_reg_p3_audio_enable;            // 0xAB0520
            //'h526: O_cfg_rdata <= O_reg_p3_line_step[11:8];         // 0xAB0524
            //'h527: O_cfg_rdata <= O_reg_p3_line_step[7:0];          // 0xAB0524
            default: O_cfg_rdata <= 'd0;
        endcase

endmodule
`default_nettype wire

